There is a consistent pattern in how engineering teams structure their PCB simulation workflow — and it tends to produce the same result, time and again.
The board returns from fabrication. Bring-up reveals something unexpected — a supply voltage that drops under load, an interface that fails at maximum data rate, or a component that resets under specific operating conditions. The engineers spend days narrowing down the problem. Simulation eventually confirms the cause. The fix is straightforward. The respin takes three weeks.
This is the standard progression. It is accepted as normal. It reflects a PCB simulation workflow built around verification rather than prevention — and it doesn't have to be this way. The same simulation that confirms a respin would also have prevented it if it had been run three weeks earlier.
The Cost of Discovering Errors Too Late
A board respin has direct costs: fabrication, assembly, engineering time. It also has indirect costs that are harder to quantify — delayed launches, resources pulled from other projects, and the cumulative stress of debugging under time pressure.
The problems causing respins are almost always structural. Impedance mismatches, PDN resonances, IR drop hotspots, return path discontinuities — these are systematic issues resulting from design decisions made during schematic capture and layout. They are not random errors. They are predictable consequences of specific choices. Most of them can be identified before routing begins — but only if analysis is built into the process at the right time.
The reason they are discovered late is not that they are difficult to detect. It is that simulation is typically treated as a verification step at the end of the design process — something done to confirm that a completed layout is correct. At that stage, fixing a structural issue often means significant parts of the board must be rerouted.
It is a PCB simulation workflow problem, not a tool problem. The tools to catch these errors earlier exist and are widely available. The question is when in the process they are used.
Restructuring PCB Simulation Workflow
Moving signal and power integrity analysis earlier in the process does not mean running a full simulation before any layout exists. It means making simulation an input for design decisions — not just an evaluation of their outcome. The goal is to catch structural issues while there is still time to address them without a respin.
In practice, restructuring the PCB simulation workflow looks like a series of concrete changes in the work sequence.
Impedance and stackup are defined before routing. Target impedance for critical nets, calculated against the actual board stackup, should be established before a trace is placed. It takes an hour. It establishes routing requirements that — if followed consistently — prevent impedance mismatch errors entirely.
PDN design and capacitor selection are finalized during the schematic phase. PDN impedance analysis can be run with a schematic model — before layout geometry exists. This identifies resonance risks and enables optimization of capacitor values and types before placement. Moving this analysis forward by just one design phase typically eliminates an entire category of power integrity errors.
IR drop is modeled before copper is poured. A current density model, built from the schematic and initial component placement, identifies high-resistance paths. Correcting trace widths before routing is complete is a routing decision. Correcting after fabrication is a respin.
Return path continuity is assessed during component placement. Plane splits, via transitions, and layer assignments affecting return current flow can be evaluated and corrected during placement — before routing begins. At the routing stage, fixing a reference plane issue can mean rerouting multiple layers.
None of these steps require an entirely new PCB simulation workflow. They require the same workflow, rearranged. Each step moves the same analysis to an earlier point in the process. The simulation does not change. The cost of acting on the result does.
What It Requires
Running simulation earlier requires tools that support pre-layout or parallel analysis — not just post-layout verification. Cadence Sigrity and the signal integrity features in OrCAD X are designed for just this — they enable PDN analysis, impedance modeling, and return path assessment at the stages where it is most cost-effective to act on the results.
It also requires simulation to be part of the standard design workflow — not something initiated only when a problem is suspected. For many teams, the barrier is not competence or tools. It is habit.
Beyond tools, the shift requires alignment between the layout engineer and the SI analyst at stages where they typically do not interact. In many teams, the signal integrity review occurs after the layout is finished — because that is the point where the layout engineer considers the work complete and passes it on. Moving the review forward means building explicit checkpoints into the workflow rather than relying on a late hand-off.
A pattern we regularly see when teams restructure their process: the first pre-layout PDN analysis takes longer than expected because the team must make explicit decisions they previously made intuitively. The second run is faster. By the third board, the previous checks have become routine.
The Practical Argument
The ten most common signal and power integrity issues causing PCB design failures — impedance mismatch, crosstalk, PDN resonance, IR drop, ground bounce, return path discontinuities, via stubs, insufficient decoupling, timing skew, and EMI leakage — can all be caught before fabrication. Most of them can be caught before routing is complete. [Internal link: article about the 10 SI/PI issues]
For teams that have restructured their process, the effect is seen in two places: fewer findings during final verification and shorter troubleshooting cycles when issues arise. When an error is caught during schematic review, there is typically one engineer, one requirement, and one decision. When it appears during board bring-up, there is a debugging session, a root-cause investigation, a fix, and a respin.
It is not an argument for a more complicated design process. It is an argument for putting the right checks at the right time in the existing one.
The PCB simulation workflow is the same whether you run it during schematic review or during board bring-up. The cost of acting on the result is not.
If your team works with Cadence Sigrity, OrCAD X, or similar SI/PI tools and wants to integrate simulation into the design flow from the start, Nordcad's specialists can review your current process and identify where analysis can be moved forward. We work with engineering teams throughout the Nordics on exactly this.
